The technique disclosed herein relates to a semiconductor device, and particularly relates to a stacked via structure used for multiple layers of interconnects.
In recent years, advances in miniaturization of semiconductor devices in a semiconductor manufacturing process have been accompanied by demands for higher integration and higher speed of semiconductor integrated circuit devices. In association with the miniaturization, miniaturization of an interconnect width, an interconnect thickness, and a via diameter has been achieved, resulting in an increase in density of current flowing through a metal interconnect.
In a metal interconnect, a phenomenon called “electromigration (hereinafter referred to as “EM”)” occurs due to collision among electrons and metal atoms upon current application. If current is applied for a long period of time, an interconnect(s) or a via(s) may be disconnected, and therefore defects influencing reliability may occur. For such a reason, there is a design limitation which is the allowable density of current flowing through a metal interconnect. However, since the current density is increased with the miniaturization, a difficulty in suppressing the current density within the allowable range has been increased.
In a semiconductor integrated circuit device such as a large scale integration (LSI) semiconductor device, there is a disadvantage that EM resistance is reduced due to current concentration in a via part connecting metal interconnects of different layers. For example, a method for overcoming the disadvantage by a layout in which a via length is increased to relieve the current concentration in the via part has been proposed (see Japanese Patent Publication No. H10-214893).